CV-51002
2015.12.04
69
POR Specifications
POR Specifications
Table 54: Fast and Standard POR Delay Specification for Cyclone V Devices
POR Delay
Minimum
Maximum
12(73)
Unit
ms
Fast
4
Standard
100
300
ms
Related Information
MSEL Pin Settings
Provides more information about POR delay based on MSEL pin settings for each configuration scheme.
FPGA JTAG Configuration Timing
Table 55: FPGA JTAG Timing Parameters and Values for Cyclone V Devices
Symbol
Description
Min
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock period
30, 167(74)
TCK clock high time
TCK clock low time
14
14
1
—
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
—
3
—
5
—
11(75)
14(75)
tJPCO
—
—
tJPZX
JTAG port high impedance to valid output
(73)
(74)
(75)
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.
A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns
if it equals 1.8 V.
Cyclone V Device Datasheet
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