Processor Configuration Registers
2.13.5
PM_PDWN_config_C0–Power-down Configuration
Register
This register defines the power-down (CKE-off) operation – power-down mode, idle
timer and global / per rank decision.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
40B0–40B3h
00000000h
RW-L
Size:
32 bits
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:13
RO
0h
Reserved (RSVD)
Global power-down (GLPDN)
1 = When this bit is set, the power-down decision is global for
channel.
12
RW-L
0b
Uncore
0 = When this bit is clear, a separate decision is taken for each
rank.
Power-down mode (PDWN_mode)
Selects the mode of power-down:
0h = No Power-Down
1h = APD
2h = PPD
3h = APD+PPD
4h = Reserved
5h = Reserved
6h = PPD_DLLoff
11:8
RW-L
0h
Uncore
7h = APD+PPD_DLLoff
8h–Fh = Reserved
Note: When selecting DLL-off or APD-DLL off, DIMM MR0
register bit 12 (PPD) must equal 0.
Note: When selecting APD, PPD or APD-PPD DIMM MR0
register bit 12 (PPD) must equal 1.
The value 0x0 (no power-down) is a don't care.
Power-down idle timer (PDWN_idle_counter)
7:0
RW-L
00h
Uncore
This field defines the rank idle period in DCLK cycles that causes
power-down entrance.
Datasheet, Volume 2
243
INTEL [ INTEL ]
