Processor Configuration Registers
2.13.6
TC_RFP_C0—Refresh Parameters Register
This register provides the refresh parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
4294–4297h
0000980Fh
RW-L
Size:
32 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:18
RO
0h
Reserved (RSVD)
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00 = Double refresh rate when DRAM is WARM/HOT.
01 = Force double self refresh regardless of temperature.
10 = Disable double self refresh regardless of temperature.
11 = Reserved
17:16
15:12
RW-L
RW-L
00b
Uncore
Uncore
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is
9)
9h
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible.
Refresh high priority WM (Refresh_HP_WM)
11:8
7:0
RW-L
RW-L
8h
Uncore
Uncore
tREFI count level that turns the refresh priority to high (default is
8)
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
cycles
0Fh
2.13.7
TC_RFTP_C0—Refresh Timing Parameters Register
This register provides the Refresh timing parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
4298–429Bh
46B41004h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
9 * tREFI
31:25
RW-L
23h
Uncore
Uncore
Period of minimum between 9*tREFI and tRAS maximum
(normally 70 us) in 1024 * DCLK cycles (default is 35h).
Refresh execution time (tRFC)
Time of refresh – from beginning of refresh until next ACT or
refresh is allowed (in DCLK cycles, default is 180h).
24:16
15:0
RW-L
RW-L
0B4h
tREFI period in DCLK cycles (tREFI)
This field defines the average period between refreshes, and the
rate that tREFI counter is incremented (in DCLK cycles, default is
4100h).
1004h
Uncore
244
Datasheet, Volume 2
INTEL [ INTEL ]
