Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4404–4407h
86104344h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
tWTR in DCLK cycles (tWTR)
Delay from internal WR transaction to internal RD transaction.
The minimum delay is 4 DCLK cycles, whereas the maximum
delay is 8 DCLK cycles.
15:12
RW-L
4h
Uncore
tCKE in DCLK cycles (tCKE)
CKE minimum pulse width in DCLK cycles. The minimum value is
3 DCLK cycles, whereas the maximum value is the actual value of
tXP.
11:8
7:4
RW-L
RW-L
RW-L
3h
4h
4h
Uncore
Uncore
Uncore
tRTP in DCLK cycles (tRTP)
Minimum delay from CAS-RD to PRE. The minimum delay is 4
DCLK cycles, whereas the maximum delay is 8 DCLK cycles.
tRRD in DCLK cycles (tRRD)
tRRD is the minimum delay between two ACT commands
targeted to different banks in the same rank. The minimum delay
is 4 DCLK cycles, whereas the maximum delay is 7 cycles.
3:0
2.14.3
SC_IO_LATENCY_C1—IO Latency configuration Register
This register identifies the I/O latency per rank, and I/O compensation (global).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4428–442Bh
000E0000h
RW-L
32 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:22
21:16
15:12
11:8
7:4
RO
0h
0Eh
0h
Reserved (RSVD)
RW-L
RW-L
RW-L
RW-L
RW-L
Uncore
Uncore
Uncore
Uncore
Uncore
Round trip – I/O compensation (RT_IOCOMP)
IO latency Rank 1 DIMM 1 (IOLAT_R1D1)
IO latency Rank 0 DIMM 1 (IOLAT_R0D1)
IO latency Rank 1 DIMM 0 (IOLAT_R1D0)
IO latency Rank 0 DIMM 0 (IOLAT_R0D0)
0h
0h
3:0
0h
Datasheet, Volume 2
247
INTEL [ INTEL ]
