Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4400–4403h
00146666h
RW-L
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
CAS latency in DCLK cycles (tCL)
Delay from CAS command to data out of DDR pins. This does not
define the sample point in the I/O. This is defined by training in
round-trip register and other registers, because this is also
affected by board delays
Delay from CAS command to data out of DDR pins. Range is 5–
15.
11:8
RW-L
6h
Uncore
Note: This does not define the sample point in the IO. This is
defined by training in round-trip register and other
registers, because this is also affected by board delays.
Note: The range of 12–15 is not yet defined by JEDEC, will be
tested only when such definition will exist.
tRP in DCLK cycles (tRP)
PRE to ACT same bank delay range is 4–15 DCLK cycles
7:4
3:0
RW-L
RW-L
6h
6h
Uncore
Uncore
tRCD in DCLK cycles (tRCD)
ACT to CAS (RD or WR) same bank delay tRCD range is between
4 and 15.
2.14.2
TC_RAP_C1—Timing of DDR – Regular Access Parameters
Register
This register provides the regular timing parameters in DCLK cycles.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4404–4407h
86104344h
RW-L
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
1n 2N or 3N selection (CMD_stretch)
This field defines the operation mode of the command
00 = 1N operation
10 = 2N operation
11 = 3N operation
31:30
RW-L
10b
0b
Uncore
Uncore
Command 3-state options (CMD_3st)
This bit defines when command & address bus is driving.
0 = Drive when channel is active. Tri-stated when all ranks are in
CKE-off or when memory is in SR or deeper.
29
RW-L
1 = Command bus is always driving. When no new valid
command is driven, previous command & address is driven
tWR in DCLK cycles (tWR)
Write recovery time. The range is 5 to 16 DCLK cycles.
28:24
23:16
RW-L
RW-L
06h
10h
Uncore
Uncore
tFAW in DCLK cycles (tFAW)
Four-activate window is the time frame in which maximum of 4
ACT commands to the same rank are allowed. The minimum
value is 4*tRRD, whereas the maximum value is 63 DCLK cycles.
246
Datasheet, Volume 2
INTEL [ INTEL ]
