Processor Configuration Registers
2.13
MCHBAR Registers in Memory Controller—Channel
0 Registers
Table 2-16. MCHBAR Registers in Memory Controller – Channel 0 Register Address Map
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–3FFFh
RSVD
TC_DBP_C0
TC_RAP_C0
RSVD
Reserved
0h
RO
RW-L
RW-L
—
4000–4003h
4004–4007h
4008–4027h
Timing of DDR – bin parameters
Timing of DDR – regular access parameters
Reserved
00146666h
86104344h
—
SC_IO_LATE IO Latency configuration
NCY_C0
4028–402Bh
402C–409Fh
40A0–40A3h
000E0000h
—
RW-L
—
RSVD
Reserved
PM_PDWN_c Power-down configuration register
onfig_C0
00000000h
RW-L
40A4–40B3h
40BC–40C7h
40D0–4293h
4294–4297h
4298–429Bh
429C–438Fh
RSVD
RSVD
Reserved
—
—
RO
Reserved
0h
—
RSVD
Reserved
—
TC_RFP_C0
Refresh Parameters
0000980Fh
46B41004h
—
RW-L
RW-L
—
TC_RFTP_C0 Refresh Timing Parameters
RSVD Reserved
Datasheet, Volume 2
239