Processor Configuration Registers
2.13.3
SC_IO_LATENCY_C0—IO Latency configuration Register
This register identifies the I/O latency per rank, and I/O compensation (global).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
4028–402Bh
000E0000h
RW-L
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:22
21:16
15:12
11:8
7:4
RO
0h
0Eh
0h
Reserved (RSVD)
RW-L
RW-L
RW-L
RW-L
RW-L
Uncore
Uncore
Uncore
Uncore
Uncore
Round trip – I/O compensation (RT_IOCOMP)
IO latency Rank 1 DIMM 1 (IOLAT_R1D1)
IO latency Rank 0 DIMM 1 (IOLAT_R0D1)
IO latency Rank 1 DIMM 0 (IOLAT_R1D0)
IO latency Rank 0 DIMM 0 (IOLAT_R0D0)
0h
0h
3:0
0h
2.13.4
TC_SRFTP_C0–Self Refresh Timing Parameters Register
This register is for the Self-refresh timing parameters.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
42A4–42A7h
0100B200h
RW-L
Size:
32 bits
BIOS Optimal Default
0h
Reset
Value
RST/
PWR
Bit
Access
Description
(tMOD)
This field is the time between MRS command and any other
command in DCLK cycles.
Actual value is 8 + programmed-Value. For example, when
programming 4 in the field, tMOD value is actually 12 DCLK
cycles
31:28
RW-L
0h
Uncore
27:26
25:16
RO
0h
Reserved (RSVD)
(tZQOPER)
RW-L
100h
Uncore
Uncore
Defines the period required for ZQCL after SR exit
(tXS_offset)
Delay from SR exit to the first DDR command
tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns.
Range is between 3 and 11 DCLK cycles.
15:12
11:0
RW-L
RW-L
Bh
(tXSDLL)
Delay between DDR SR exit and the first command that requires
data RD/WR from DDR is in the range of 128 to 1024 DCLK
cycles, though all JEDEC DDRs assume 512 DCLK cycles
200h
Uncore
242
Datasheet, Volume 2
INTEL [ INTEL ]
