Processor Configuration Registers
2.13.1
TC_DBP_C0—Timing of DDR – Bin Parameters Register
This register defines the BIN timing parameters for safe logic – tRCD, tRP, tCL, tWCL
and tRAS.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC0
4000–4003h
00146666h
RW-L
32 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
RO
Description
31:24
23:16
0h
Reserved (RSVD)
tRAS in DCLK cycles (tRAS)
Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles
RW-L
14h
Uncore
Uncore
Write CAS latency in DCLK cycles (tWCL)
Delay from CAS WR command to data valid on DDR pins. Range
is 5–15. The value 5 should not be programmed if the DEC_WRD
bit in TC_RWP register is set.
15:12
RW-L
6h
CAS latency in DCLK cycles (tCL)
This field is the Delay from CAS command to data out of DDR
pins.
This does not define the sample point in the IO. This is defined by
training in round-trip register and other registers, because this is
also affected by board delays.
Delay from CAS command to data out of DDR pins. Range is 5–
15.
11:8
RW-L
6h
Uncore
Notes:
1.
2.
This does not define the sample point in the IO. This is
defined by training in round-trip register and other
registers, because this is also affected by board delays.
The range of 12–15 is not yet defined by JEDEC, will be
tested only when such definition will exist.
tRP in DCLK cycles (tRP)
PRE to ACT same bank delay range is 4–15 DCLK cycles
7:4
3:0
RW-L
RW-L
6h
6h
Uncore
Uncore
tRCD in DCLK cycles (tRCD)
ACT to CAS (RD or WR) same bank delay tRCD range is between
4 and 15.
240
Datasheet, Volume 2
INTEL [ INTEL ]
