Processor Configuration Registers
2.14
MCHBAR Registers in Memory Controller –
Channel 1
Table 2-17. MCHBAR Registers in Memory Controller – Channel 1 Register Address Map
Register
Symbol
Address
Register Name
Reset Value
Access
0–43FFh
RSVD
Reserved
0h
RO
4400–4403h
TC_DBP_C1
Timing of DDR – bin parameters
00146666h
RW-L
Timing of DDR – regular access
parameters
4404–4407h
4408–4427h
4428–442Bh
442C–44AFh
44B0–44B3h
TC_RAP_C1
RSVD
86104344h
—
RW-L
—
Reserved
SC_IO_LATENCY_ IO Latency configuration
C1
000E0000h
—
RW-L
—
RSVD
Reserved
PM_PDWN_config Power-down configuration register
_C1
00000000h
RW-L
44BC–44C7h
44D0–4693h
4694–4697h
4698–469Bh
469C–469Fh
46A0–46A3h
46A4–46A7h
46A8–478Fh
RSVD
RSVD
Reserved
0h
RO
—
Reserved
—
TC_RFP_C1
TC_RFTP_C1
RSVD
Refresh parameters
Refresh timing parameters
Reserved
0000980Fh
46B41004h
00000000h
00000000h
0100B200h
—
RW-L
RW-L
RW-L
RW-L
RW-L
—
RSVD
Reserved
TC_SRFTP_C1
RSVD
Self Refresh Timing Parameters
Reserved
2.14.1
TC_DBP_C1—Timing of DDR – Bin Parameters Register
This register defines the BIN timing parameters for safe logic – tRCD, tRP, tCL, tWCL,
and tRAS.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR MC1
4400–4403h
00146666h
RW-L
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23:16
RO
0h
Reserved (RSVD)
tRAS in DCLK cycles (tRAS)
Minimum ACT to PRE timing Range is 10 to 40 DCLK cycles.
RW-L
14h
Uncore
Uncore
Write CAS latency in DCLK cycles (tWCL)
Delay from CAS WR command to data valid on DDR pins. Range
is 5–15. The value 5 should not be programmed if the DEC_WRD
bit in TC_RWP register is set.
15:12
RW-L
6h
Datasheet, Volume 2
245
INTEL [ INTEL ]
