Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
98–99h
0002h
RWS, RWS-V
16 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Hardware Autonomous Speed Disable (HASD)
When set to 1b this bit disables hardware from changing the
link speed for reasons other than attempting to correct
unreliable link operation by reducing link speed.
5
RWS
0b
0b
Powergood
Powergood
Enter Compliance (EC)
Software is permitted to force a link to enter Compliance mode
at the speed indicated in the Target Link Speed field by setting
this bit to 1b in both components on a link and then initiating a
hot reset on the link.
4
RWS
Target Link Speed (TLS)
For Downstream ports, this field sets an upper limit on link
operational speed by restricting the values advertised by the
upstream component in its training sequences.
0001b = 2.5 Gb/s Target Link Speed
0010b = 5 Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a
speed included in the Supported Link Speeds field, the result is
undefined.
3:0
RWS
2h
Powergood
The Reset Value of this field is the highest link speed supported
by the component (as reported in the Supported Link Speeds
field of the Link Capabilities Register) unless the corresponding
platform / form factor requires a different Reset Value.
For both Upstream and Downstream ports, this field is used to
set the target compliance mode speed when software is using
the Enter Compliance bit to force a link into compliance mode.
2.12.28 LSTS2—Link Status 2 Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
9A–9Bh
0000h
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
15:1
RO
0h
Reserved (RSVD)
Current De-emphasis Level (CURDELVL)
When the Link is operating at 5 GT/s speed, this reflects the level
of de-emphasis.
1b = -3.5 dB
0
RO-V
0b
Uncore
0b = -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
238
Datasheet, Volume 2
INTEL [ INTEL ]
