Processor Configuration Registers
2.12.4
DMIPVCCTL—DMI Port VC Control Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
C–Dh
0000h
RW, RO
16 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:4
RO
0h
000b
0b
Reserved (RSVD)
VC Arbitration Select (VCAS)
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
The value 000b when written to this field will indicate the VC
arbitration scheme is hardware fixed (in the root complex). This
field cannot be modified when more than one VC in the LPVC
group is enabled.
000 = Hardware fixed arbitration scheme, such as Round Robin
Others = Reserved
3:1
RW
Uncore
Uncore
See the PCI express specification for more details.
0
RO
Reserved for Load VC Arbitration Table (LVCAT)
2.12.5
DMIVC0RCAP—DMI VC0 Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
10–13h
00000001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23
RO
RO
RO
00h
0h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
Reserved (RSVD)
22:16
00h
Uncore
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is
applicable but is not set within the TLP Header will be
rejected as an Unsupported Request.
15
RO
0b
Uncore
Uncore
14:8
7:0
RO
RO
0h
Reserved (RSVD)
Port Arbitration Capability (PAC)
Having only bit 0 set indicates that the only supported arbitration
scheme for this VC is non-configurable hardware-fixed.
01h
220
Datasheet, Volume 2
INTEL [ INTEL ]
