Processor Configuration Registers
2.12.6
DMIVC0RCTL—DMI VC0 Resource Control Register
This register controls the resources associated with PCI Express* Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
14–17h
8000007Fh
RO, RW
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Virtual Channel 0 Enable (VC0E)
31
RO
RO
RO
RO
1b
0h
Uncore
For VC0, this is hardwired to 1 and read only as VC0 can never be
disabled.
30:27
26:24
23:20
Reserved (RSVD)
Virtual Channel 0 ID (VC0ID)
This field assigns a VC ID to the VC resource. For VC0, this is
hardwired to 0 and read only.
000b
0h
Uncore
Reserved (RSVD)
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. A valid value for this field is a number
corresponding to one of the asserted bits in the Port Arbitration
Capability field of the VC resource. Because only bit 0 of that field
is asserted.
19:17
RW
000b
Uncore
This field will always be programmed to '1'.
16:8
7
RO
RO
0h
0b
Reserved (RSVD)
Uncore
Uncore
Traffic Class m / Virtual Channel 0 Map (TCMVC0M)
Traffic Class / Virtual Channel 0 Map (TCVC0M)
This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC
values.
For example, when bit 7 is set in this field, TC7 is mapped to this
VC resource. When more than one bit in this field is set, it
indicates that multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
6:1
RW
RO
3Fh
1b
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.
0
Uncore
Datasheet, Volume 2
221
INTEL [ INTEL ]
