Processor Configuration Registers
2.11.20 EQPRESET6_7—Equalization Preset 6/7 Register
This register contains coefficients for Preset 6 and 7.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
DCC–DCFh
36200E06h
RW
Size:
32 bits
BIOS Optimal Default
0h
Reset
Value
RST/
PWR
Bit
Access
Description
31:6
5:0
RO
0h
Reserved (RSVD)
Preset 6 Precursor Coefficient (PRECUR6):
Precursor coefficient for Preset 6.
RW
06h
Uncore
2.11.21 EQCFG—Equalization Configuration Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/MMR
DD8–DDBh
00000000h
RW
Size:
32 bits
BIOS Optimal Default
00000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:2
RO
0h
0
Reserved (RSVD)
Disable Margining (MARGINDIS)
When set, it will disable Tx margining during Polling.Compliance
and Recovery.
1
0
RW
RO
Uncore
0
Reserved (RSVD)
216
Datasheet, Volume 2
INTEL [ INTEL ]
