Processor Configuration Registers
2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register
This register reports the Virtual Channel specific status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
26–27h
0002h
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
15:2
RO
0h
1b
0h
Reserved (RSVD)
Virtual Channel 1 Negotiation Pending (VC1NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
Software may use this bit when enabling or disabling the VC. This
bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever
the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
1
0
RO-V
Uncore
RO
Reserved (RSVD)
2.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
28–2Bh
00000001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23
RO
RO
RO
00h
0h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
Reserved (RSVD)
22:16
00h
Uncore
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is
applicable but is not set within the TLP Header will be
rejected as an Unsupported Request.
15
RO
0b
Uncore
Uncore
14:8
7:0
RO
RO
0h
Reserved (RSVD)
01h
Reserved for Port Arbitration Capability (PAC)
224
Datasheet, Volume 2
INTEL [ INTEL ]
