Processor Configuration Registers
2.12.2
DMIPVCCAP1—DMI Port VC Capability Register 1
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
4–7h
00000000h
RO, RW-O
32 bits
Size:
BIOS Optimal Default
0000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:7
RO
0h
Reserved (RSVD)
Low Priority Extended VC Count (LPEVCC)
This field indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
6:4
RO
000b
Uncore
Uncore
The value of 0 in this field implies strict VC arbitration.
3
RO
0h
Reserved (RSVD)
Extended VC Count (EVCC)
This field indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.
2:0
RW-O
000b
2.12.3
DMIPVCCAP2—DMI Port VC Capability Register 2
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
8–Bh
00000000h
RO
32 bits
0000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23:8
7:0
RO
RO
RO
00h
0h
Uncore
Reserved for VC Arbitration Table Offset (VCATO)
Reserved (RSVD)
00h
Uncore
Reserved for VC Arbitration Capability (VCAC)
Datasheet, Volume 2
219
INTEL [ INTEL ]
