Processor Configuration Registers
2.12.7
DMIVC0RSTS—DMI VC0 Resource Status Register
This register reports the Virtual Channel specific status.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
1A–1Bh
0002h
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
15:2
RO
0h
1b
0h
Reserved (RSVD)
Virtual Channel 0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever
the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state.
1
0
RO-V
Uncore
It is cleared when the link successfully exits the FC_INIT2 state.
BIOS Requirement: Before using a Virtual Channel, software
must check whether the VC Negotiation Pending fields for that
Virtual Channel are cleared in both Components on a Link.
RO
Reserved (RSVD)
2.12.8
DMIVC1RCAP—DMI VC1 Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
1C–1Fh
00008001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23
RO
RO
RO
00h
0h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
Reserved (RSVD)
22:16
00h
Uncore
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = When set, any transaction for which the No Snoop attribute
is applicable but is not set within the TLP Header will be
rejected as an Unsupported Request.
15
RO
1b
Uncore
Uncore
14:8
7:0
RO
RO
0h
Reserved (RSVD)
Port Arbitration Capability (PAC)
Having only bit 0 set indicates that the only supported arbitration
scheme for this VC is non-configurable hardware-fixed.
01h
222
Datasheet, Volume 2
INTEL [ INTEL ]
