Processor Configuration Registers
2.12
Direct Media Interface Base Address Registers
(DMIBAR)
Table 2-15. DMIBAR Register Address Map (Sheet 1 of 2)
Address
Offset
Register Symbol
Register Name
Reset Value
Access
0–3h
DMIVCECH
DMIPVCCAP1
DMIPVCCAP2
DMIPVCCTL
RSVD
DMI Virtual Channel Enhanced Capability
DMI Port VC Capability Register 1
DMI Port VC Capability Register 2
DMI Port VC Control
04010002h
00000000h
00000000h
0000h
RO
RO, RW-O
RO
4–7h
8–Bh
C–Dh
RW, RO
RO
E–Fh
Reserved
0h
10–13h
14–17h
18–19h
1A–1Bh
1C–1Fh
20–23h
24–25h
26–27h
28–2Bh
2C–2Fh
30–31h
32–33h
34–37h
38–3Bh
3C–3Dh
3E–3Fh
40–43h
44–47h
48–4Fh
50–53h
54–57h
58–5Bh
5C–5Fh
60–63h
64–67h
68–6Bh
6C–6Fh
70–7Fh
80–83h
DMIVC0RCAP
DMIVC0RCTL
RSVD
DMI VC0 Resource Capability
DMI VC0 Resour ce Control
Reserved
00000001h
8000007Fh
0h
RO
RO, RW
RO
DMIVC0RSTS
DMIVC1RCAP
DMIVC1RCTL
RSVD
DMI VC0 Resource Status
DMI VC1 Resource Capability
DMI VC1 Resource Control
Reserved
0002h
RO-V
RO
00008001h
01000000h
0h
RO, RW
RO
DMIVC1RSTS
DMIVCPRCAP
DMIVCPRCTL
RSVD
DMI VC1 Resource Status
DMI VCp Resource Capability
DMI VCp Resource Control
Reserved
0002h
RO-V
RO
00000001h
02000000h
0h
RO, RW
RO
DMIVCPRSTS
DMIVCMRCAP
DMIVCMRCTL
RSVD
DMI VCp Resource Status
DMI VCm Resource Capability
DMI VCm Resource Control
Reserved
0002h
RO-V
RO
00008000h
07000080h
0h
RW, RO
RO
DMIVCMRSTS
DMIRCLDECH
DMIESD
DMI VCm Resource Status
DMI Root Complex Link Declaration
DMI Element Self Description
Reserved
0002h
RO-V
RO
08010005h
01000202h
0h
RO, RW-O
RO
RSVD
DMILE1D
RSVD
DMI Link Entry 1 Description
Reserved
00000000h
0h
RW-O, RO
RO
DMILE1A
DMI Link Entry 1 Address
DMI Link Upper Entry 1 Address
DMI Link Entry 2 Description
Reserved
00000000h
00000000h
00000000h
0h
RW-O
RW-O
RO, RW-O
RO
DMILUE1A
DMILE2D
RSVD
DMILE2A
DMI Link Entry 2 Address
Reserved
00000000h
00000000h
0h
RW-O
RW-O
RO
RSVD
RSVD
Reserved
RSVD
Reserved
00010006h
RO
Link Capabilities
RW-O, RO,
RW-OV
84–87h
88–89h
LCAP
LCTL
0001AC41h
0000h
Link Control
RW, RW-V
Datasheet, Volume 2
217
INTEL [ INTEL ]
