Electrical Specifications
Figure 2-13. VID Step Times
n
n-1
m
m+1
VID
...
Tc
VCC(max)
Ta
Tb
Td
VCC(min)
Ta = VID Down to Valid VCC(max)
Tb = VID Down to Valid VCC(min)
Tc
= VID Up to Valid VCC(max)
Td = VID Up to Valid VCC(min)
Table 2-29. SMBus and SPDBus Signal Group AC Timing Specifications
Notes
1, 2
Symbol
Parameter
Min
Max
Unit
Figure
Transmitter and Receiver Timings
F
SMBCLK Frequency
SMBCLK Period
10
10
4
100
100
kHz
µs
µs
µs
µs
µs
µs
ns
ns
V
SMB
TCK
t
t
t
t
SMBCLK High Time
SMBCLK Low Time
SMBus Rise Time
SMBus Fall Time
2-14
2-14
2-14
2-14
2-15
2-14
2-14
LOW
HIGH
R
4.7
1
3
0.3
4.5
3
F
T
SMBus Output Valid Delay
SMBus Input Setup Time
SMBus Input Hold Time
SMBus Vil
0.1
250
AA
t
t
SU;DAT
HD;DAT
0
Vil, SMBus
Vih, SMBus
Vol, SMBus
-0.3
Vcc33 x 0.3
Vcc33 + 0.5
0.4
SMBus Vih
Vcc33 x 0.7
V
SMBus Vol Vcc >2.5
SMBus Vol Vcc <= 2.5
V
0.2
V
t
t
t
t
Bus Free Time between
Stop and Start Condition
4.7
4.0
4.7
4.0
µs
2-14
2-14
2-14
2-14
4, 5
BUF
Hold Time after Repeated
Start Condition
µs
µs
µs
HD;STA
SU;STA
SU;STD
Repeated Start Condition
Setup Time
Stop Condition Setup Time
Notes:
1.
2.
These parameters are based on design characterization and are not tested.
All AC timings for the SMBus signals are referenced at V
pins. Refer to Figure 2-14.
or V
and measured at the processor
IL_MAX
IL_MIN
3.
Rise time is measured from (V
- 0.15V) to (V
+ 0.15V). Fall time is measured from (0.9 *
IH_MIN
IL_MAX
VCC33) to (V
- 0.15V).
IL_MAX
4.
5.
Minimum time allowed between request cycles.
Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next
transaction.
46
Datasheet Volume 1 of 2
INTEL [ INTEL ]
