Electrical Specifications
Figure 2-20. Intel QPI System Interface Electrical Test Setup for Validating
TX + Worst-Case Interconnect Specifications
W o rs t-C a s e In te rc o n n e c t
Id e a l
L o a d s
S ilic o n
T x b it
(D a ta )
T x
P a c k a g e
Id e a l
L o a d s
S ilic o n
T x b it
(C lo c k )
L o s s le s s In te rc o n n e c t P h a s e
M a tc h e d to D a ta B it In te rc o n n e c t
Figure 2-21. Differential Clock Waveform
Overshoot
BCLK1
VH
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tp
Tp = T1: BCLK[1:0] period
50
Datasheet Volume 1 of 2