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325119-001 参数 Datasheet PDF下载

325119-001图片预览
型号: 325119-001
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔® Xeon®处理器E7-8800 / 2800分之4800产品系列 [Intel® Xeon® Processor E7-8800/4800/2800 Product Families]
分类和应用:
文件页数/大小: 174 页 / 3951 K
品牌: INTEL [ INTEL ]
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Electrical Specifications  
Table 2-25. Miscellaneous DC Specifications  
Notes  
1
Pin  
Parameter  
Min  
Typ  
Max  
Units  
SKTID[2:0]  
Input Low Voltage  
Input High Voltage  
Leakage limit low  
Leakage limit high  
Leakage limit low  
Leakage limit high  
<0.54 VIOC  
V
3
>0.7 VCC  
V
2
3
2
3
5
uA  
mA  
mA  
uA  
4.2  
2.6  
5
THERMALERT  
Notes:  
1.  
2.  
3.  
Unless otherwise noted, all specifications in this table apply to all processor frequencies.  
Recommended strapping high is 1K - 10K Ω.  
Recommended strapping low is <100 Ω.  
2.8  
AC Specifications  
The processor timings specified in this section are defined at the processor pads.  
Therefore, proper simulation of the signals is the only means to verify proper timing  
and signal quality.  
Table 2-26 through Table 2-28 list the AC specifications associated with the processor.  
See Chapter 5 for signal definitions.  
The timings specified in this section should be used in conjunction with the processor  
signal integrity models provided by Intel. Intel QPI, SMI and sideband layout guidelines  
are also available in the appropriate platform design guidelines.  
Note:  
Care should be taken to read all notes associated with a particular timing parameter.  
Table 2-26. System Reference Clock AC Specifications (Sheet 1 of 2)  
Symbol  
(SSC-off)  
Parameter  
Min  
Nom  
Max  
Unit  
Figure  
Notes  
System Reference Clock  
frequency  
f
133.29  
133.33  
133.37  
MHz  
REFCLK  
System Reference Clock  
frequency  
f
(SSC-on)  
132.62  
175  
133.33  
133.37  
700  
MHz  
ps  
REFCLK  
T
T
Rise time, fall time.  
1, 2  
Rise, Fall  
%
period  
3
T
Duty cycle of reference clock.  
40  
50  
60  
Refclk-Dutycycle  
ER  
,
Differential Rising and falling  
edge rates  
3, 4  
Refclk-diff-Rise  
1
4
V/ns  
ER  
Refclk-diff-Fall  
C CK  
I-  
Clock Input Capacitance  
Differential Input Low Voltage  
Differential Input High Voltage  
Absolute Crossing Point  
0.2  
1.0  
pF  
V
VL  
-0.15  
3
VH  
0.15  
0.25  
V
3
V
0.35  
0.55  
V
1, 5, 6  
5, 7  
cross  
0.25 +  
0.55 +  
V
(rel)  
Relative Crossing Point  
0.5*(VH  
-
0.5*(VH  
-
avg  
cross  
avg  
0.700)  
-
0.700)  
0.14  
V
Delta  
V
variation  
cross  
-
-
V
V
1, 5, 8  
1, 9  
cross  
V
(Absolute  
max  
Overshoot)  
Single-ended maximum voltage  
-
1.15  
Datasheet Volume 1 of 2  
43  
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