Electrical Specifications
Figure 2-16. FLASHROM Timing Waveform
FLASHROM_CS
tCS_AS
tCS_DE
FLASHROM_CLK
FLASHROM_DATO
FLASHROM_DATI
tDELAY
tSETUP
tHOLD
Table 2-31.TAP Signal Group AC Timing Specifications
Notes
1, 2
Symbol
Parameter
Min
Max
Unit
Figure
Transmitter and Receiver Timings
F
T
T
T
T
TCK Frequency
66
MHz
2-17
3
TAP
TCK Period
15
7.5
7.5
7.5
30
ns
ns
ns
ns
ns
p
TDI, TMS Setup Time
TDI, TMS Hold Time
TDO Clock to Output Delay
TRST_N Assert Time
2-17
2-17
2-17
2-18
4, 5
4, 6
6
S
H
24
X
7
Notes:
1.
2.
3.
4.
5.
Not 100% tested. These parameters are based on design characterization.
It is recommended that TMS be asserted while TRST_N is being deasserted.
This specification is based on the capabilities of the ITP-XDP debug port tool, not on processor silicon.
Referenced to the rising edge of TCK.
Specification for a minimum swing defined between TAP V to V . This assumes a minimum edge rate of
0.5 V/ns.
T-
T+
6.
7.
Referenced to the falling edge of TCK.
TRST_N must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
Figure 2-17. TAP Valid Delay Timing Waveform
Tp
V
TCK
Tx
Ts
Th
V
Valid
Signal
Tp = TAP Frequency
Tx = TDO Clock to Output Delay
Ts = TDI, TMS Setup Time
Th = TDI, TMS Hold Time
V = 0.5 * VIO
48
Datasheet Volume 1 of 2
INTEL [ INTEL ]
