Electrical Specifications
Notes:
1.
2.
3.
These values are based on driving a 50Ω transmission line into a 50Ω±pullup.
Deterministic reset.
Inspection range is VIL Max to VIH Min. When a signal ledge presents between VIL and VIH region,
measure the first edge rate from VIL (or VIH) to the first inflection point, then measure the second edge
rate from the second inflection point to VIH (or VIL) and divide the sum of the two edge rates by two, to
generate the final edge rate number.
4.
5.
Error signals are 0.1 V/ns if non-monotonic, and 0.05 V/ns if monotonic.
For production platforms, reset determinism is not required.
Table 2-28. VID Signal Group AC Specifications
Notes
1, 2
T # Parameter
Min
Max
Unit
Figure
VID Step Time
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
2-29
VID Down Transition to Valid V
(min)
2-28,2-29
2-28,2-29
2-28,2-29
2-28,2-29
CCP
VID Up Transition to Valid V
(min)
CCP
VID Down Transition to Valid V
VID Up Transition to Valid V
(max)
CCP
(max)
CCP
Notes:
1.
See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design
Guidelines for addition information.
2.
Platform support for VID transitions is required for the processor to operate within specifications.
Figure 2-11. RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion
SYSCLK_N
SYSCLK
Tsetup
Thold
V
IH
V
IL
RESET_N
Note: Deterministic RESET_N is defined for RESET_N deassertion only (coming out of RESET_N)
Figure 2-12. THERMTRIP_N Power Down Sequence
TA
THERMTRIP_N
VCC, VCACHE
TA = THERMTRIP_N assertion until VCC and VCACHE removal
Datasheet Volume 1 of 2
45
INTEL [ INTEL ]
