Electrical Specifications
Figure 2-14. SMBus Timing Waveform
t
t
F
t
HD;STA
R
t
LOW
Clk
t
t
SU;STO
t
t
t
HIGH
t
HD;STA
SU;STA
HD;DAT
SU;DAT
Data
t
BUF
S
S
P
P
STOP
START
START
STOP
Figure 2-15. SMBus Valid Delay Timing Waveform
SM_CLK
TAA
DATA VALID
SM_DAT
DATA OUTPUT
Table 2-30. FLASHROM Signal Group AC Timing Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
0
66.67
MHz
F
FLASHROM_CLK Frequency
FLASHROM_DATI Edge Rate
FLASHROM
0.5
0.7
10
V/ns
V/ns
ns
1
2
Slew
Slew
DATAI
DATAO
FLASHROM_DATO Edge Rate
2.3
FLASHROM_CS[3:0]_N assertion
before first FLASHROM_CLK
2-16
2-16
t
t
CS_AS
FLASHROM_CS[3:0]_N deassertion
after last FLASHROM_CLK
12
ns
CS_DE
FLASHROM_DATI setup time
FLASHROM_DATI hold time
FLASHROM_DATO Valid Delay
6
0
ns
ns
ns
2-16
2-16
2-16
t
t
t
SETUP
HOLD
–2.0
2.0
DELAY
Notes:
1.
All input edge rates are specified between V (max) and V (min), and output edge rates are specified
between V (max) and V (min).
IL IH
OL
OH
2.
These values are based on driving a 50Ω transmission line into a 50Ω±pullup.
Datasheet Volume 1 of 2
47
INTEL [ INTEL ]
