Electrical Specifications
Figure 2-10. Input Device Hysteresis
VIO
Maximum VP
PECI High Range
Minimum VP
Maximum VN
Minimum
Hysteresis Signal Range
Valid Input
Minimum VN
PECI Ground
PECI Low Range
2.7
DC Specifications
Table 2-24. TAP, Strap Pins, Error, Powerup, RESET, Thermal, VID Signal Group DC
Specifications
Notes
1
Symbol
Parameter
Min
Typ
Max
0.54 V
IOF
Units
V
Input Low Voltage
Input High Voltage
-0.1
V
V
2,3
IL
*
V
0.86
V
IOF
2
IH
*
V
* R / (R +
ON
sys_term
2,5
IOC
ON
V
Output Low Voltage
V
OL
R
)
V
Output High Voltage
V
V
2
OH
IOC
Rtt
On Die Pull Up Termination
42.5
0.5
50
57.5
2.9
Ohm
T
time from SYSCLK pin
3
4
CO
T
ns
ps
CO
till signal valid at output
Control Sideband Input
signals with respect to
SYSCLK
Setup
Time
900
900
Control Sideband Input
signals with respect to
SYSCLK
4
Hold
Time
ps
POC/
Reset
Setup
Time
Power-On Configuration
Setup Time
2
SYSCLK
POC/
Reset
Hold
Power-On Configuration
Hold Time
108
8
SYSCLK
Time
Control Sideband Buffer on
Resistance
R
18
Ohm
ON
I
Input Leakage Current
± 200
μA
6
LI
Notes:
1.
2.
3.
4.
5.
6.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The V referred to in these specifications refers to instantaneous V
IO
IO.
Based on a test load of 50Ω to V
IOC.
Specified for synchronous signals.
R
is the termination on the system, not part of the processor.
SYS_TERM
®
Intel Trusted Execution Technology for Servers Input Leakage Current Maximum is ±50 uA.
42
Datasheet Volume 1 of 2
INTEL [ INTEL ]
