Electrical Specifications
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor die and DRAM temperatures, perform
processor manageability functions, and manage processor interface tuning and
diagnostics.
2.6.1
DC Characteristics
The PECI interface operates at a nominal voltage set by VIOC. The set of DC electrical
specifications shown in Table 2-23 is used with devices normally operating from a VIOC
interface supply. VIOC nominal levels will vary between processor families. All PECI
devices will operate at the VIOC level determined by the processor installed in the
system. For specific nominal VIOC levels, refer to Table 2-23.
Table 2-23. PECI DC Electrical Limits
Notes
1
Symbol
Definition and Conditions
Min
Max
+ 0.15
IOC
Units
V
Input Voltage Range
Hysteresis
-0.150
V
V
V
V
V
in
V
0.1 * V
IOC
hysteresis
V
V
Negative-edge threshold voltage
Positive-edge threshold voltage
Low level output sink
0.275 * V
0.50 * V
IoC
2
n
IOC
IOC
0.55 * V
0.5
0.725 * V
1.0
2
p
IOC
I
mA
µA
sink
(V = 0.25 * V
)
OL
IOC
High impedance state leakage to
3
V
I
N/A
50
IOC
leak+
(V
= V
)
OL
leak
High impedance leakage to GND
(V = V
3
I
N/A
N/A
25
10
µA
pF
leak-
)
OH
leak
C
Bus capacitance per node
4,5
bus
Signal noise immunity above
300 MHz
V
0.1 * V
N/A
V
p-p
noise
IOC
Note:
1.
2.
V
supplies the PECI interface. PECI behavior does not affect V
min/max specifications.
IOC
IOC
It is expected that the PECI driver will take in to account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.15V to 0.275*V for the low level and
IOC
0.725*V
to V
+0.15 for the high level).
IOC
IOC
3.
4.
The leakage specification applies to powered devices on the PECI bus.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
5.
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
2.6.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 2-10 as a guide for input buffer design.
Datasheet Volume 1 of 2
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