LPC Interface Bridge Registers (D31:F0)
13.8.1.7
BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh
Attribute:
R/W
Default Value:
Lockable:
00h
No
Core
Size:
8-bit
Usage:
ACPI, Legacy
Power Well:
Bit
Description
STORAGE_BREAK_EN — R/W.
0 = Serial ATA traffic will not act as a break event.
1 = Serial ATA traffic acts as a break event, even if the BM_STS-ZERO_EN and
POPUP_EN bits are set. Serial ATA master activity will cause BM_STS to be set and
will cause a break from C3/C4.
7
6
PCIE_BREAK_EN — R/W.
0 = PCI Express* traffic will not act as a break event.
1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and
POPUP_EN bits are set. PCI Express master activity will cause BM_STS to be set
and will cause a break from C3/C4.
PCI_BREAK_EN — R/W.
0 = PCI traffic will not act as a break event.
5
4:3
2
1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits
are set. PCI master activity will cause BM_STS to be set and will cause a break
from C3/C4.
Reserved
EHCI_BREAK_EN — R/W.
0 = EHCI traffic will not act as a break event.
1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN
bits are set. EHCI master activity will cause BM_STS to be set and will cause a
break from C3/C4.
UHCI_BREAK_EN — R/W.
0 = UHCI traffic will not act as a break event.
1
0
1 = USB traffic from any of the internal UHCIs acts as a break event, even if the
BM_STS-ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause
BM_STS to be set and will cause a break from C3/C4.
HDA_BREAK_EN — R/W.
0 = Intel® High Definition Audio traffic will not act as a break event.
1 = Intel High Definition Audio traffic acts as a break event, even if the BM_STS-
ZERO_EN and POPUP_EN bits are set. Intel High Definition Audio master activity
will cause BM_STS to be set and will cause a break from C3/C4.
458
Datasheet
INTEL [ INTEL ]
