LPC Interface Bridge Registers (D31:F0)
13.8.1.6
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0)
Offset Address: AAh
Attribute:
Size:
Usage:
R/W
Default Value:
Lockable:
00h
No
Core
8-bit
ACPI, Legacy
Power Well:
This register is used to enable C-state related modes.
Bit
Description
7
6
Reserved
Slow-C4 Exit Enable —When 1, this bit enables the Slow-C4 Exit functionality.
5:4
Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the ICH10
waits for from the deassertion of DPRSLPVR to the deassertion of STP_CPU#. This
provides a programmable time for the processor’s voltage to stabilize when exiting
from a C4 state. This thus changes the value for t266a.
Bits
00b
01b
10b
11b
t266amin t266amax
Comment
3:2
95 µs
22 µs
34 µs
101 µs
28 µs
40 µs
Default
Value used for “Fast” VRMs
Value used for “Fast” VRMs
Reserved
DPSLP-TO-MCH Message— R/W. This field selects the DPSLP# deassertion to
(G)MCH message time (t270). Normally this value is determined by the
CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,
then the values in this register have higher priority. It is software’s responsibility to
program these fields in a consistent manner.
Bits
00b
01b
10b
11b
t270
1:0
Use value is CPU_PLL_LOCK_TIME field (default is 30 µs)
20 µs
15 µs
10 µs
Datasheet
457
INTEL [ INTEL ]
