LPC Interface Bridge Registers (D31:F0)
13.8.3.1
PM1_STS—Power Management 1 Status Register
I/O Address:
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
Attribute:
R/WC
Default Value:
Lockable:
Power Well:
Size:
16-bit
No
Usage:
ACPI or Legacy
Bits 0–7: Core,
Bits 8–15: Resume,
except Bit 11 in RTC
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then the ICH10 will generate a Wake Event. Once back in an S0 state (or if
already in an S0 state when the event occurs), the ICH10 will also generate an SCI if
the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.
Note:
Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
Bit
Description
Wake Status (WAK_STS) — R/WC. This bit is not affected by hard resets caused
by a CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (via the SLP_EN
bit) and an enabled wake event occurs. Upon setting this bit, the ICH10 will
transition the system to the ON state.
If the AFTERG3_EN bit is not set and a power failure occurs without the SLP_EN bit
set, the system will return to an S0 state when power returns, and the WAK_STS bit
will not be set.
15
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit
having been set, the system will go into an S5 state when power returns, and a
subsequent wake event will cause the WAK_STS bit to be set. Note that any
subsequent wake event would have to be caused by either a Power Button press, or
an enabled wake event that was preserved through the power failure (enable bit in
the RTC well).
PCI Express Wake Status (PCIEXPWAK_STS) — R/WC.
0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during
the write or the PME message received indication has not been cleared in the
root port, then the bit will remain active (i.e. all inputs to this bit are level-
sensitive).
1 = This bit is set by hardware to indicate that the system woke due to a PCI
Express wakeup event. This wakeup event can be caused by the PCI Express
WAKE# pin being active or receipt of a PCI Express PME message at a root port.
This bit is set only when one of these events causes the system to transition
from a non-S0 system power state to the S0 system power state. This bit is set
independent of the state of the PCIEXP_WAKE_DIS bit.
14
Note: This bit does not itself cause a wake event or prevent entry to a sleeping
state. Thus if the bit is 1 and the system is put into a sleeping state, the system will
not automatically wake.
13:12
Reserved
462
Datasheet
INTEL [ INTEL ]
