LPC Interface Bridge Registers (D31:F0)
13.8.2
APM I/O Decode
Table 13-10 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
Table 13-10. APM Register Map
Address Mnemonic
Register Name
Default
Type
B2h
B3h
APM_CNT
APM_STS
Advanced Power Management Control Port
Advanced Power Management Status Port
00h
00h
R/W
R/W
13.8.2.1
APM_CNT—Advanced Power Management Control Port Register
I/O Address:
Default Value:
Lockable:
B2h
00h
No
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Power Well:
Core
Bit
Description
Used to pass an APM command between the OS and the SMI handler. Writes to this
port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
7:0
13.8.2.2
APM_STS—Advanced Power Management Status Port Register
I/O Address:
Default Value:
Lockable:
B3h
00h
No
Attribute:
Size:
Usage:
R/W
8-bit
Legacy Only
Power Well:
Core
Bit
Description
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
register and is not affected by any other register or function (other than a PCI reset).
7:0
460
Datasheet
INTEL [ INTEL ]
