LPC Interface Bridge Registers (D31:F0)
13.8.1.4
GEN_PMCON_LOCK- General Power Management Configuration Lock
Register
Offset Address: A6h
Attribute:
Size:
Usage:
RO, R/WLO
8-bit
ACPI
Default Value:
Lockable:
00h
No
Core
Power Well:
Bit
Description
Unlocked C-State Transition — RO. This bit is set by hardware when a processor
power state (C-State) transition deeper than C2 occurs and the C-
STATE_CONFIG_LOCK bit is not set. This bit is cleared by PLTRST# and is not
writable by software.
7
6:3
Reserved
SLP_S4# Stretching Policy Lock-Down — R/WLO. When set to 1, this bit locks
down the SLP_S4# Minimum Assertion Width, the SLP_S4# Assertion Stretch
Enable (Corporate Only), the Disable SLP_S4# Stretching after G3 (Corporate
Only) and SLP_S4# Assertion Stretch Enable (Consumer Only) bits in the
GEN_PMCON_3 register, making them read-only.
2
1
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored.
This bit is cleared by platform reset.
ACPI_BASE_LOCK — R/WLO. When set to 1, this bit locks down the ACPI Base
Address Register (ABASE) at offset 40h. The Base Address Field becomes read-
only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored. Once locked by writing 1, the only way to clear this bit is to
perform a platform reset.
C-STATE_CONFIG_LOCK — R/WLO. When set to 1, this bit locks down the C-State
configuration parameters. The following configuration bits become read-only when
this bit is set:
• IA64_EN (GEN_PMCON_1, bit 6)
• C4_DISABLE (GEN_PMCON_1, bit 12)
0
• CPU_PLL_LOCK_TIME (GEN_PMCON_2, bits 6:5)
• The entire C4 Timing Control Register (C4_TIMING_CNT)
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored. Once locked by writing 1, the only way to clear this bit is to
perform a platform reset.
C
Datasheet
455
INTEL [ INTEL ]
