LPC Interface Bridge Registers (D31:F0)
13.8.1.5
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0)
Offset Address: A9h
Attribute:
Size:
Usage:
R/W
Default Value:
Lockable:
00h
No
Core
8-bit
ACPI, Legacy
Power Well:
This register is used to enable C-state related modes.
Bit
Description
7
SCRATCHPAD (SP) — R/W.
6:5
Reserved
Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME
bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.
0 = The ICH10 will not attempt to automatically return to a previous C3 or C4 state.
1 = When this bit is a 1 and ICH10 observes that there are no bus master requests, it
can return to a previous C3 or C4 state.
NOTE: This bit is separate from the PUME bit to cover cases where latency issues
permit POPUP but not POPDOWN.
4
3
Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH10 behaves like
ICH5, in that bus master traffic is a break event, and it will return from C3/C4 to C0
based on a break event. See Chapter 5.13.5 for additional details on this mode.
0 = The ICH10 will treat Bus master traffic a break event, and will return from C3/C4 to
C0 based on a break event.
1 = When this bit is a 1 and ICH10 observes a bus master request, it will take the
system from a C3 or C4 state to a C2 state and auto enable bus masters. This will
let snoops and memory access occur.
Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.
0 = The ICH10 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from
PCI, PCI Express* and internal bus masters.
1 = When this bit is a 1, ICH10 will not set the BM_STS if there is bus master activity
from PCI, PCI Express and internal bus masters.
NOTES:
2
1.
2.
3.
If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the
BM_STS bit will remain set. Software will still need to clear the BM_STS bit.
It is expected that if the PUME bit (this register, bit 3) is set, the
BM_STS_ZERO_EN bit should also be set.
BM_STS will be set by LPC DMA or LPC masters, even if BM_STS_ZERO_EN is
set.
1:0
Reserved
456
Datasheet
INTEL [ INTEL ]
