LPC Interface Bridge Registers (D31:F0)
13.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Attribute:
Size:
R/W, R/WC
16-bit
Default Value:
0000h Consumer Only
0200h Corporate Only
No
Lockable:
Usage:
Power Well:
ACPI, Legacy
RTC, SUS
Bit
Description
PME B0 S5 Disable (PME_B0_S5_DIS)— R/W. When set to '1', this bit blocks
wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
When cleared (default), wake events from PME_B0_STS are allowed in S5 if
PME_B0_EN = '1'.
Wakes from power states other than S5 are not affected by this policy bit.
The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table
below:
Y = Wake; N = Don't wake; B0 = PME_B0_EN; OV = WOL Enable Override
15
(Corporate
Only)
B0/OV
00
S1/S3/S4
S5
N
N
N
01
11
01
Y (LAN only)
Y (LAN only)
N
Y (all PME B0 sources)
Y (all PME B0 sources)
This bit is cleared by the RTCRST# pin.
15
(Consumer Reserved
Only)
MAC Power Down During WOL Disable — R/W.
14
0 = MAC power down WOL is enabled if the hardware and software requirements
(Corporate
Only)
are met.
1 = Integrated MAC remains powered whenever external suspend rails are
powered.
WOL Enable Override — R/W.
0 = WOL policies are determined by PMEB0 enable bit and appropriate LAN status
bits
1 = Enable integrated LAN to wake the system in S5 only regardless of the value in
the PME_B0_EN bit in the GPE0_EN register.
13
(Corporate
Only)
This bit is cleared by the RTCRST# pin.
Disable SLP_S4# Stretching after G3:
0 = Enables stretching on SLP_S4# in conjunction with SLP_S4# Assertion Stretch
Enable (bit 3) and the Minimum Assertion Width (bits 5:4)
12
(Corporate 1 = Disables stretching on SLP_S4# regardless of the state of the SLP_S4#
Only)
Assertion Stretch Enable (bit 3).
This bit is cleared by the RTCRST# pin.
NOTE: This field is RO when the SLP_Sx# Stretching Policy Lock- Down bit is set.
452
Datasheet
INTEL [ INTEL ]
