LPC Interface Bridge Registers (D31:F0)
13.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0h
Attribute:
Size:
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
Default Value:
Lockable:
0000h
No
Usage:
Power Well:
Bit
Description
15:13
Reserved
C4 Disable — R/W. This bit disables the C4 feature.
0 = Enables C4
1 = Disables C4.
12
When C4 Disable is 1:
• I/O reads to the LVL4 register will be retried normally, but with no other action
• All C4 transition attempts are disabled, overriding C4onC3 and Pop-Down
transition.
BMBUSY# Select (BMSEL)— R/W. This bit along with GPIO_USE_SEL[0] bit enables
selection of BM_BUSY#/GPIO0 function on ICH pin as shown below:
11
GPIO_USE_SEL[0]
BMSEL
Pin Function
GPIO0
1
0
0
X
0
1
BMBUSY#
Reserved
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit
10
9
to go active.
1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to
go active.
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
8
7
6
Reserved
Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when
software does a LVL3 read, the ICH10 transitions to the C4 state.
Ignore Stop-Grant - R/W. Software sets this bit to indicate that the ICH must not
(Corporate wait for the Stop Grant (aka REQ_C2) cycle. This bit must be set for iA64
Only)
processors and CSI processors.
6
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,
(Consumer not an IA_32 processor. This may be used in various state machines where there
Only)
are behavioral differences.
5
(Corporate Reserved
Only)
448
Datasheet
INTEL [ INTEL ]
