LPC Interface Bridge Registers (D31:F0)
Bit
Description
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
5
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the
processor power.
(Consumer
Only)
NOTE: CPUSLP# will go active on entry to C3 and C4 states even if this bit is not
set.
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE
+ 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by
PLTRST#).
4
3
Reserved
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. ICH10 drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and
STP_PCI# signals.
2
NOTE: When the SLP_EN# bit is set, the ICH10 drives the CLKRUN# signal low
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control
the rate at which periodic SMI# is generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
1:0
Datasheet
449
INTEL [ INTEL ]
