LPC Interface Bridge Registers (D31:F0)
13.7.4
COPROC_ERR—Coprocessor Error Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
F0h
00h
No
Attribute:
Size:
Power Well:
WO
8-bits
Core
Bits
Description
Coprocessor Error (COPROC_ERR) — WO. Any value written to this register will
cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit (Chipset Config Registers:Offset
31FFh: bit 1 for Consumer Family and Offset 31FEh: bit 9 for Corporate family) must be
1.
7:0
13.7.5
RST_CNT—Reset Control Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
CF9h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:4
Reserved
Full Reset (FULL_RST) — R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
0 = ICH10 will keep SLP_S3#, SLP_S4# and SLP_S5# high.
1 = ICH10 will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3 – 5 seconds.
3
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
in response to SYSRESET#, PWROK#, and Watchdog timer reset sources.
Reset CPU (RST_CPU) — R/W. When this bit transitions from a 0 to a 1, it initiates a
hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
2
System Reset (SYS_RST) — R/W. This bit is used to determine a hard or soft reset to
the processor.
0 = When RST_CPU bit goes from 0 to 1, the ICH10 performs a soft reset by activating
INIT# for 16 PCI clocks.
1
0
1 = When RST_CPU bit goes from 0 to 1, the ICH10 performs a hard reset by activating
PLTRST# and SUS_STAT# active for about 5-6 milliseconds. In this case,
SLP_S3#, SLP_S4# and SLP_S5# state (assertion or de-assertion) depends on
FULL_RST bit setting. The ICH10 main power well is reset when this bit is 1. It also
resets the resume well bits (except for those noted throughout the EDS).
Reserved
446
Datasheet
INTEL [ INTEL ]
