LPC Interface Bridge Registers (D31:F0)
13.1.5
RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h
Attribute:
Size:
RO
8 bits
Default Value:
See bit description
Bit
Description
Revision ID (RID) — RO. Refer to the Intel® I/O Controller Hub (ICH10) Family
Specification Update for the value of the Revision ID Register
7:0
13.1.6
13.1.7
PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h
Attribute:
Size:
RO
8 bits
Default Value:
00h
Bit
Description
7:0
Programming Interface — RO.
SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah
Attribute:
Size:
RO
8 bits
Default Value:
01h
Bit
Description
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
7:0
01h = PCI-to-ISA bridge.
13.1.8
13.1.9
BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh
Attribute:
Size:
RO
8 bits
Default Value:
06h
Bit
Description
Base Class Code — RO. This field is an 8-bit value that indicates the type of device for
the LPC bridge.
7:0
06h = Bridge device.
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Attribute:
Size:
RO
8 bits
Default Value:
00h
Bit
Description
7:3
2:0
Master Latency Count (MLC) — Reserved.
Reserved.
Datasheet
391
INTEL [ INTEL ]
