LPC Interface Bridge Registers (D31:F0)
13.1.4
PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06h–07h
Attribute:
Size:
Power Well:
RO, R/WC
16-bit
Core
Default Value:
Lockable:
0210h
No
Note:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
Detected Parity Error (DPE) — R/WC. This bit is set when the LPC bridge detects a
parity error on the internal backbone. The bit is set even if the PCICMD.PERE bit
(D31:F0:04, bit 6) is 0.
15
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE)— R/WC. This bit is set when the LPC bridge signals a
system error to the internal SERR# logic.
14
13
Master Abort Status (RMA) — R/WC.
0 = Unsupported request status not received.
1 = The bridge received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
12
0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Signaled Target Abort (STA) — R/WC.
0 = Target abort Not generated on the backbone.
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
11
DEVSEL# Timing Status (DEV_STS) — RO.
10:9
01 = Medium Timing.
Data Parity Error Detected (DPED) — R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
8
• LPC bridge receives a completion packet from the backbone from a previous
request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal
backbone.
7
6
5
Reserved.
66 MHz Capable (66MHZ_CAP) — Reserved – bit has no meaning on the internal
backbone.
4
3
Capabilities List (CLIST) — RO. Capability list exists on the LPC bridge.
Interrupt Status (IS) — RO. The LPC bridge does not generate interrupts.
Reserved.
2:0
390
Datasheet
INTEL [ INTEL ]
