LPC Interface Bridge Registers (D31:F0)
13.1.1
13.1.2
VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h–01h
Attribute:
Size:
Power Well:
RO
16-bit
Core
Default Value:
Lockable:
8086h
No
Bit
Description
15:0
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h–03h
Attribute:
Size:
Power Well:
RO
16-bit
Core
Default Value:
Lockable:
See bit description
No
Bit
Description
Device ID — RO. This is a 16-bit value assigned to the Intel® ICH10 LPC bridge.
Refer to the Intel® I/O Controller Hub (ICH10) Family for the value of the Device ID
Register.
15:0
13.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h–05h
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
Default Value:
Lockable:
0007h
No
Bit
Description
15:10 Reserved
9
8
7
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
0 = No action is taken when detecting a parity error.
1 = Enables the ICH10 LPC bridge to respond to parity errors detected on backbone
interface.
6
5
4
3
2
1
0
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
Datasheet
389
INTEL [ INTEL ]
