LPC Interface Bridge Registers (D31:F0)
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Attribute:
Size:
RO
8 bits
Default Value:
80h
Bit
Description
7
Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.
6:0
13.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch–2Fh
Default Value: 00000000h
Attribute:
Size:
R/WO
32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
Bit
Description
Subsystem ID (SSID) — R/WO. This is written by BIOS. No hardware action taken on
this value.
31:16
Subsystem Vendor ID (SSVID) — R/WO. This is written by BIOS. No hardware
action taken on this value.
15:0
13.1.12 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h–43h
Attribute:
Size:
R/W, RO
32 bit
ACPI, Legacy
Core
Default Value:
Lockable:
00000001h
No
Usage:
Power Well:
This register sets base address for ACPI I/O registers, GPIO registers, and TCO I/O
registers. These registers can be mapped anywhere in the 64-KB I/O space on
128-Byte boundaries.
Bit
Description
31:16
Reserved
Base Address — R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
TCO logic. This is placed on a 128-byte boundary.
15:7
6:1
0
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate I/O space.
392
Datasheet
INTEL [ INTEL ]
