LPC Interface Bridge Registers (D31:F0)
Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
Offset
Mnemonic
Register Name
Default
Type
HPET 2
74h-75h
H2BDF
00F8h
RW
Bus:Device:Function(H2BDF)
HPET 3
76h-77h
78h-79h
7Ah-7Bh
7Ch-7Dh
7Eh-7Fh
H3BDF
H4BDF
H5BDF
H6BDF
H7BDF
00F8h
00F8h
00F8h
00F8h
00F8h
RW
RW
RW
RW
RW
Bus:Device:Function(H3BDF)
HPET 4
Bus:Device:Function(H4BDF)
HPET 5
Bus:Device:Function(H5BDF)
HPET 6
Bus:Device:Function(H6BDF)
HPET 7
Bus:Device:Function(H7BDF)
80h
LPC_I/O_DEC
LPC_EN
I/O Decode Ranges
0000h
R/W
R/W
R/W
R/W
R/W
R/W
82h–83h
84h–87h
88h–8Bh
8Ch–8Eh
90h–93h
LPC I/F Enables
0000h
GEN1_DEC
GEN2_DEC
GEN3_DEC
GEN4_DEC
LPC I/F Generic Decode Range 1
LPC I/F Generic Decode Range 2
LPC I/F Generic Decode Range 3
LPC I/F Generic Decode Range 4
00000000h
00000000h
00000000h
00000000h
LPC Generic Memory Range
(Corporate Only)
98h-9Bh
A0h–CFh
LGMR
00000000h
R/W
Power Management (See
Section 13.8.1)
D0h–D3h
D4h–D5h
D8h–D9h
FWH_SEL1
FWH_SEL2
Firmware Hub Select 1
Firmware Hub Select 2
00112233h
4567h
R/W, RO
R/W
FWH_DEC_EN1 Firmware Hub Decode Enable 1
FFCFh
R/W, RO
R/WLO,R/W,
RO
DCh
E0h-E1h
E2h
BIOS_CNTL
FDCAP
FDLEN
BIOS Control
00h
0009h
0Ch
Feature Detection Capability ID
RO
RO
Feature Detection Capability
Length
E3h
FDVER
FDVCT
RCBA
Feature Detection Version
Feature Vector
10h
RO
See
Description
E4h-EBh
F0h-F3h
RO
Root Complex Base Address
00000000h
R/W
388
Datasheet
INTEL [ INTEL ]
