LPC Interface Bridge Registers (D31:F0)
13.1.15 GC—GPIO Control Register (LPC I/F — D31:F0)
Offset Address: 4Ch
Attribute:
Size:
R/W
8 bit
Default Value:
00h
Bit
Description
7:5
Reserved.
GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed
to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.
4
0 = Disable.
1 = Enable.
3:1
Reserved.
GPIO Lockdown Enable (GLE) — R/W. This bit enables lockdown of the following
GPIO registers:
• Offset 00h: GPIO_USE_SEL
• Offset 04h: GP_IO_SEL
• Offset 0Ch: GP_LVL
• Offset 30h: GPIO_USE_SEL2
• Offset 34h: GP_IO_SEL2
• Offset 38h: GP_LVL2
0
• Offset 40h: GPIO_USE_SEL3 (Corporate Only)
• Offset 44h: GP_IO_SEL3 (Corporate Only)
• Offset 48h: GP_LVL3 (Corporate Only)
• Offset 60h: GP_RST_SEL
0 = Disable.
1 = Enable.
When this bit is written from a 1-to-0 an SMI# is generated, if enabled. This ensures
that only SMM code can change the above GPIO registers after they are locked down.
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Datasheet
INTEL [ INTEL ]
