LPC Interface Bridge Registers (D31:F0)
13.1.13 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0)
Offset Address: 44h
Attribute:
Size:
R/W
Default Value:
Lockable:
00h
No
8 bit
Usage:
ACPI, Legacy
Core
Power Well:
Bit
Description
ACPI Enable (ACPI_EN) — R/W.
0 = Disable.
7
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
ACPI power management function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and are not affected by this bit.
6:3
Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
Bits
000b
001b
010b
011b
SCI Map
IRQ9
IRQ10
IRQ11
2:0
Reserved
IRQ20 (Only available if APIC
enabled)
100b
101b
IRQ21 (Only available if APIC
enabled)
When the interrupt is mapped to APIC interrupts 9, 10, or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC interrupts
20 through 23, the APIC should be programmed for active-low reception.
13.1.14 GPIOBASE—GPIO Base Address Register (LPC I/F —
D31:F0)
Offset Address: 48h–4Bh
Attribute:
Size:
R/W, RO
32 bit
Default Value:
00000001h
Bit
Description
31:16
15:7
6:1
Reserved. Always 0.
Base Address (BA) — RW. Provides the 128 bytes of I/O space for GPIO.
Reserved. Always 0
0
RO. Hardwired to 1 to indicate I/O space.
Datasheet
393
INTEL [ INTEL ]
