LPC Interface Bridge Registers (D31:F0)
13 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the ICH10 resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units (EHCI, UHCI, etc.) are
described in their respective sections.
13.1
PCI Configuration Registers (LPC I/F—D31:F0)
Note:
Address locations that are not shown should be treated as Reserved.
.
Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset
Mnemonic
Register Name
Vendor Identification
Default
Type
00h–01h
VID
8086h
RO
See register
description
02h–03h
DID
Device Identification
RO
04h–05h
06h–07h
PCICMD
PCISTS
PCI Command
PCI Status
0007h
0210h
R/W, RO
R/WC, RO
See register
description
08h
RID
Revision Identification
RO
09h
0Ah
PI
SCC
Programming Interface
Sub Class Code
00h
01h
RO
RO
0Bh
BCC
Base Class Code
Primary Latency Timer
Header Type
06h
RO
0Dh
PLT
00h
RO
0Eh
HEADTYP
SS
80h
RO
2Ch–2Fh
40h–43h
44h
Sub System Identifiers
ACPI Base Address
ACPI Control
00000000h
00000001h
00h
R/WO
R/W, RO
R/W
PMBASE
ACPI_CNTL
GPIOBASE
GC
48h–4Bh
4C
GPIO Base Address
GPIO Control
00000001h
00h
R/W, RO
R/W
60h–63h
64h
PIRQ[n]_ROUT PIRQ[A–D] Routing Control
SIRQ_CNTL Serial IRQ Control
PIRQ[n]_ROUT PIRQ[E–H] Routing Control
80808080h
10h
R/W
R/W, RO
R/W
68h–6Bh
6Ch–6Dh
80808080h
00F8h
LPC_IBDF
H0BDF
IOxAPIC Bus:Device:Function
R/W
HPET 0
70h-71h
72h-73h
00F8h
00F8h
RW
RW
Bus:Device:Function(H0BDF)
HPET 1
H1BDF
Bus:Device:Function(H1BDF)
Datasheet
387
INTEL [ INTEL ]
