LPC Interface Bridge Registers (D31:F0)
13.1.16 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute:
PIRQC – 62h, PIRQD – 63h
R/W
Default Value:
Lockable:
80h
No
Size:
8 bit
Core
Power Well:
Bit
Description
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS
when setting up for I/O APIC interrupt delivery mode.
6:4
Reserved
IRQ Routing — R/W. (ISA compatible.)
Value
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
IRQ
Reserved
Reserved
Reserved
IRQ3
Value
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
IRQ
Reserved
IRQ9
IRQ10
3:0
IRQ11
IRQ4
IRQ12
IRQ5
Reserved
IRQ14
IRQ6
IRQ7
IRQ15
Datasheet
395
INTEL [ INTEL ]
