Chipset Configuration Registers
10.1.8
V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 001A–001Bh
Attribute:
Size:
RO
16-bit
Default Value:
0000h
Bit
Description
15:2
1
Reserved
VC Negotiation Pending (NP) — RO. When set, indicates the virtual channel is still
being negotiated with ingress ports.
Port Arbitration Tables Status (ATS) — RO. There is no port arbitration table for
this VC, so this bit is reserved at 0.
0
10.1.9
V1CAP—Virtual Channel 1 Resource Capability Register
Offset Address: 001C–001Fh
Attribute:
Size:
R/WO, RO
32-bit
Default Value:
03008011h (Consumer)
00008001h (Corporate)
Bit
Description
31:24
Port Arbitration Table Offset (AT) — RO. Indicates the location of the port
arbitration table in the root complex. A value of 0h indicates the table is not present
(Corporate
Only)
31:24
Port Arbitration Table Offset (AT) — RO. Indicates the location of the port
(Consumer arbitration table in the root complex. A value of 3h indicates the table is at offset
Only)
30h.
23
Reserved
Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS
based upon the determination of the number of time slots available in the platform.
22:16
15
Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are
rejected. This VC is for isochronous transfers only.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions,
not just advanced packet switching transactions.
14
13:8
Reserved
7:0
(Corporate
Only)
Port Arbitration Capability (PAC) — RO. Indicates the port arbitration capability
is hardware-fixed.
7:0
Port Arbitration Capability (PAC) — RO. Indicates the port arbitration capability
is time-based WRR of 128 phases.
(Consumer
Only)
Datasheet
309
INTEL [ INTEL ]
