Chipset Configuration Registers
10.1.15 RCTCL—Root Complex Topology Capabilities List Register
Offset Address: 0100–0103h
Attribute:
Size:
RO
32-bit
Default Value:
1A010005h
Bit
Description
31:20
19:16
Next Capability (NEXT) — RO. Indicates the next item in the list.
Capability Version (CV) — RO. Indicates the version of the capability structure.
Capability ID (CID) — RO. Indicates this is a PCI Express* link capability section of
an RCRB.
15:0
10.1.16 ESD—Element Self Description Register
Offset Address: 0104–0107h
Attribute:
Size:
R/WO, RO
32-bit
Default Value:
00000802h
Bit
Description
Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel
ICH10.
31:24
23:16
Component ID (CID) — R/WO. Indicates the component ID assigned to this
element by software. This is written once by platform BIOS and is locked until a
platform reset.
Number of Link Entries (NLE) — RO. Indicates that one link entry (corresponding
to DMI), 6 root port entries (for the downstream ports), and the Intel High Definition
Audio device are described by this RCRB.
15:8
7:4
3:0
Reserved
Element Type (ET) — RO. Indicates that the element type is a root complex
internal link.
10.1.17 ULD—Upstream Link Descriptor Register
Offset Address: 0110–0113h
Attribute:
Size:
R/WO, RO
32-bit
Default Value:
00000001h
Bit
Description
Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to
match the port number of the (G)MCH RCRB that is attached to this RCRB.
31:24
23:16
Target Component ID (TCID) — R/WO. This field is programmed by platform BIOS
to match the component ID of the (G)MCH RCRB that is attached to this RCRB.
15:2
Reserved
1
0
Link Type (LT) — RO. Indicates that the link points to the (G)MCH RCRB.
Link Valid (LV) — RO. Indicates that the link entry is valid.
312
Datasheet
INTEL [ INTEL ]
