Chipset Configuration Registers
10.1.3
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Attribute:
Size:
RO
32-bit
Default Value:
00000001h
Bit
Description
VC Arbitration Table Offset (ATO) — RO. Indicates that no table is present for VC
arbitration since it is fixed.
31:24
23:8
7:0
Reserved
VC Arbitration Capability (AC) — RO. Indicates that the VC arbitration is fixed in
the root complex.
10.1.4
PVC—Port Virtual Channel Control Register
Offset Address: 000C–000Dh
Attribute:
Size:
RO, R/W
16-bit
Default Value:
0000h
Bit
Description
15:04
Reserved
VC Arbitration Select (AS) — R/W. Indicates which VC should be programmed in
the VC arbitration table. The root complex takes no action on the setting of this field
since there is no arbitration table.
3:1
Load VC Arbitration Table (LAT) — RO. Indicates that the table programmed
should be loaded into the VC arbitration table. This bit is defined as read/write with
always returning 0 on reads.
0
10.1.5
PVS—Port Virtual Channel Status Register
Offset Address: 000E–000Fh
Attribute:
Size:
RO
16-bit
Default Value:
0000h
Bit
Description
15:1
Reserved
VC Arbitration Table Status (VAS) — RO. Indicates the coherency status of the VC
Arbitration table when it is being updated. This field is always 0 in the root complex
since there is no VC arbitration table.
0
Datasheet
307
INTEL [ INTEL ]
