Chipset Configuration Registers
10.1.12 PAT—Port Arbitration Table (Consumer Only)
Offset Address: 0030-006Fh
Default Value:
Attribute:
Size:
64-Byte
This a 64-byte register that contains the arbitration table to be loaded into the port
arbitration table. Every 4-bits contains an entry for one of the downstream PCI
Express* ports or a 0h to indicate idle. The ports are mapped as follows:
• Port 1: Value used is 1h.
• Port 2: Value used is 2h.
• Port 3: Value used is 3h.
• Port 4: Value used is 4h.
• Port 5: Value used is 5h.
• Port 6: Value used is 6h.
• Intel High Definition Audio: Value used is Fh.
10.1.13 CIR1—Chipset Initialization Register 1
Offset Address: 0088–008Bh
Attribute:
Size:
R/WO
32-bit
Default Value:
00000000h
Bit
Description
31:21
20
Reserved
CIR1 Field 3 — R/WO. BIOS must set this bit.
19:16
15
Reserved
CIR1 Field 2 — R/WO. BIOS must set this bit.
14:13
12
Reserved
CIR1 Field 1— R/WO. BIOS must set this bit.
11:0
Reserved
10.1.14 REC—Root Error Command Register
Offset Address: 00AC–00AFh
Attribute:
Size:
R/W
32-bit
Default Value:
0000h
Bit
Description
Drop Poisoned Downstream Packets (DPDP) — R/W. Determines how
downstream packets on DMI are handled that are received with the EP field set,
indicating poisoned data:
1: This packet and all subsequent packets with data received on DMI for any VC will
have their Unsupported Transaction (UT) field set causing them to master Abort
downstream. Packets without data such as memory, IO and config read requests are
allowed to proceed.
31
0: Packets are forwarded downstream without forcing the UT field set.
30:0
Reserved
Datasheet
311
INTEL [ INTEL ]
