Chipset Configuration Registers
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 4)
Offset
Mnemonic
Register Name
I/O Trap Register 3
Default
Type
1E98-1E9Fh
IOTR3
0000000000000000h
R/W
DMI Miscellaneous Control
register
2010-2013h
DMC
00000002h
R/W
2034-2037h
3000–3000h
3100–3103h
3104–3107h
3108–310Bh
310C–310Fh
3110–3113h
3114–3117h
3118–311Bh
3140–3141h
3142–3143h
3144–3145h
3146–3147h
3148–3149h
314C–314Dh
3150–3151h
CIR7
TCTL
Chipset Initialization Register 7
TCO Control
B2B477CCh
00h
R/W
R/W
R/W, RO
RO
D31IP
D30IP
D29IP
D28IP
D27IP
D26IP
D25IP
D31IR
D30IR
D29IR
D28IR
D27IR
D26IR
D25IR
Device 31 Interrupt Pin
Device 30 Interrupt Pin
Device 29 Interrupt Pin
Device 28 Interrupt Pin
Device 27 Interrupt Pin
Device 26 Interrupt Pin
Device 25 Interrupt Pin
Device 31 Interrupt Route
Device 30 Interrupt Route
Device 29 Interrupt Route
Device 28 Interrupt Route
Device 27 Interrupt Route
Device 26 Interrupt Route
Device 25 Interrupt Route
03243200h
00000000h
10004321h
00214321h
00000001h
30000321h
00000001h
3210h
R/W
R/W
R/W
R/W
R/W
R/W
RO
0000h
3210h
R/W
R/W
R/W
R/W
R/W
3210h
3210h
3210h
3210h
31FE–31FFh
(Corporate
Only)
OIC
OIC
Other Interrupt Control
Other Interrupt Control
0000h
00h
R/W
R/W
31FF–31FFh
(Consumer
Only)
3300-3303h
3304-3307h
SBEMC3
SBEMC4
Scheduled Break Event C3
Schedule Break Event C4
00000000h
00000000h
R/W
R/W
3310–3313h
(Corporate
Only)
PRSTS
Power and Reset Status
RTC Configuration
R/W,
R/WLO
3400–3403h
3404–3407h
3410–3413h
RC
00000000h
00000000h
000000yy0h
High Precision Timer
Configuration
HPTC
GCS
R/W
R/W,
R/WLO
General Control and Status
3414–3414h
3418–341Bh
341C–341Fh
3420–3420h
3430-3433h
BUC
FD
Backed Up Control
00h
R/W
R/W
R/W
R/W
R/W
Function Disable
00000000h
00000000h
00h
CG
Clock Gating
PDSW
CIR8
Function Disable SUS Well
Chipset Initialization Register 8
00000000h
Datasheet
305
INTEL [ INTEL ]
