Chipset Configuration Registers
10.1.6
V0CAP—Virtual Channel 0 Resource Capability Register
Offset Address: 0010–0013h
Attribute:
Size:
RO
32-bit
Default Value:
00000001h
Bit
Description
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration
table since the arbitration is fixed.
31:24
23
Reserved
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and
therefore this field is not used.
22:16
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable
transactions.
15
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions,
not just advanced packet switching transactions.
14
13:8
7:0
Reserved
Port Arbitration Capability (PAC) — RO. Indicates that this VC uses fixed port
arbitration.
10.1.7
V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h
Attribute:
Size:
R/W, RO
32-bit
Default Value:
800000FFh
Bit
Description
Virtual Channel Enable (EN) — RO. Always set to 1. VC0 is always enabled and
cannot be disabled.
31
30:27
26:24
23:20
Reserved
Virtual Channel Identifier (ID) — RO. Indicates the ID to use for this virtual
channel.
Reserved
Port Arbitration Select (PAS) — R/W. Indicates which port table is being
programmed. The root complex takes no action on this setting since the arbitration is
fixed and there is no arbitration table.
19:17
Load Port Arbitration Table (LAT) — RO. The root complex does not implement
an arbitration table for this virtual channel.
16
15:8
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
7:1
0
Reserved
308
Datasheet
INTEL [ INTEL ]
